A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology



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Submitted Aug 31, 2018
Published Oct 21, 2018
10.24018/ejeng.2018.3.10.873

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A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC)  is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.
Keywords: Capacitorless DRAM Rectangular FET Buried Oxide Capacitance Silicon-on-Insulator Embedded DRAM Edram System-on Chip

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References

  1. Meng-fan chang, et al, A 130 mV “SRAM with expanded write and read margins for sub threshold applications”, IEEE Journal of Solid state circuits, vol. 46, pp. 520-529, Feb. 2011.
     Google Scholar
  2. Ashok K. Sharma, “Advanced Semiconductor Memories-Architecture, Designs, and Applications”, IEEE , Wiley Interscience, 2009.
     Google Scholar
  3. G. Wang et al, “A 0.127µm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications”, in Proceedings of IEEE International Electron Devices Meeting (IEDM-2006)-Digest of Technical Papers, pp. 1-4, Dec. 2006.
     Google Scholar
  4. Malleshaiah G. V and Srinivasaiah H. C, "Study of SRAM Cell for Balancing Read and Write Margins in Sub-100nm Technology using Noise-Curve Method”, International Journal of engineering Research and Technology (IJERT), Vol. 4 Issue 06, pp.445-449, June-2015.
     Google Scholar
  5. K. P. Muller et al, “Trench storage node technology for gigabit DRAM generations”, in proceedings of IEEE Electron Device Meeting (IEDM), pp.507-510, 1996.
     Google Scholar
  6. W. Mueller et al, “Trench DRAM technologies for the 50nm node and beyond”, in proceedings of International Symposium on VLSI Technology, Systems, and Applications, pp.1-2, 2006.
     Google Scholar
  7. Ashok k. Sharma, “Semiconductor Memories Technology Testing and Reliability”, IEEE Press, Wiley Interscience, 1997.
     Google Scholar
  8. Jyi-Tsong Lin, et al, “Transient and Thermal Analysis on Disturbance immunity for 4F2 Surrounding Gate 1T-DRAM with Wide Trenched Body”, IEEE Transactions on Electron Devices, vol. 62, pp.61-68, Jan. 2015.
     Google Scholar
  9. Jyi-Tsong Lin, et al, “Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body”, IEEE Electron Device Letters, vol. 29, pp.1222-1225, Nov. 2008.
     Google Scholar
  10. M. Gunhan Ertosun, Pawan Kapur, and Krishna C. Saraswat, “A highly scalable capacitorless double gate quantum well single transistor DRAM: 1T-QW DRAM”, IEEE Electron Device Letters, vol. 29, pp.1405-1407, Dec. 2008.
     Google Scholar
  11. H. C. Srinivasaiah, “implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM”, in proc. of IEEE international VLSI design conference, Hyderabad, India, pp. 412-417, Jan. 2012.
     Google Scholar
  12. Sentaurus TCAD manual, Synopsys, 2010.
     Google Scholar
  13. Maxim Ershov et al, “Negative capacitance effect in semiconductor devices”, IEEE Transactions on Electron devices vol. 45, pp. 2196-2206, Oct. 1998.
     Google Scholar
  14. H. C. Srinivasaiah, and Navakanta Bhat, “Characterization of sub-100nm CMOS process using screening experiment Technique”, Solid State Electronics, vol. 49, pp. 431-436, Mar. 2005.
     Google Scholar
  15. H. C. Srinivasaiah and Navakanta Bhat, “Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 742-747, June 2003.
     Google Scholar
  16. Gordon E. Moore, “Cramming more components onto integrated circuits”, Journal of Electronics, vol. 38, pp. 1-4, April 1965.
     Google Scholar
  17. R. Jacob Baker, Harry W. Li, and David E. Boyce, “CMOS circuit design, layout and simulation”, IEEE Press, 1998.
     Google Scholar
  18. Indranil De et al, “Impact of gate WF on device performance at the 50nm technology node”, Solid State Electronics, vol. 44, pp.1077-1080, 2000.
     Google Scholar